USB Specification

USB 3.0 Specifications – Physical Layer

USB 3.0 Specifications – Physical Layer

The physical layer involves the signaling technology for the SuperSpeed bus. This section will go through the electrical requirements of the USB 3.0 SuperSpeed physical layer.

Here we will also discuss the electrical layer parameters required for interoperability between USB 3.0 SuperSpeed components. Normative specifications are required. Informative specifications may assist product designers and testers in understanding the intended behavior of the SuperSpeed bus.

Physical Layer Functions

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Measurement Overview

The normative SuperSpeed eye diagram is measured through a compliance channel that represents the sum of the long channel, a short channel, and a three meter cable. This demands three separate tests for compliance. These reference channels are described in the USB SuperSpeed Compliance Methodology white paper. The eye diagram is measured using the clock recover function described below.

For the long channel case the eye diagram at the receiver is completely closed. An informative receiver equalization function is provided that is optimized to the compliance channel and is used to open the receiver eye.

This methodology allows a silicon vendor to design the channel and the component as a matched pair. It is expected that a silicon component will have layout guidelines that must be followed in order for the component to meet the overall specification and the eye diagram at the end of the compliance channel.

Note that simultaneous USB 2.0 and SuperSpeed operation is a testing requirement for compliance.

Channel Overview

A PHY is a transmitter and receiver that operate together and are located on the same component. A channel connects two PHYs together with two unidirectional differential pairs of pins for a total of four wires. The PHYs are required to be AC coupled. The AC coupling capacitors are associated with the transmitter.

Symbol Encoding

SuperSpeed uses the 8b/10b transmission code. The definition of this transmission code is identical to that specified in ANSI X3.230-1994 (also referred to as ANSI INCITS 230-1994), clause 11. As shown in below, ABCDE maps to abcdei and FGH maps to fghj.

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Serialization and Deserialization of Data

The bits of a Symbol are placed starting with bit “a” and ending with bit “j.” This is shown below.

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Normative 8b/10b Decode Rules

A Transmitter is permitted to pick any disparity when first transmitting differential data after being in an Electrical Idle state. The Transmitter shall then follow proper 8b/10b encoding rules until the next Electrical Idle state is entered.

The initial disparity for a Receiver is the disparity of the first Symbol used to obtain Symbol lock.

Disparity may also be-reinitialized if Symbol lock is lost and regained during the transmission of differential information due to a burst error event.

All following received Symbols after the initial disparity is set shall be in the proper column corresponding to the current running disparity.

Receive disparity errors do not directly cause the link to retrain.

If a disparity error or 8b/10 Decode error is detected, the physical layer shall inform the link layer.

Data Scrambling

The scrambling function is implemented using a free running Linear Feedback Shift Register (LFSR). On the Transmit side, scrambling is applied to characters prior to the 8b/10b encoding. On the receive side, descrambling is applied to characters after 8b/10b decoding. The LFSR is reset whenever a COM symbol is sent or received.

The LFSR is graphically represented in Figure 6-7 . Scrambling or unscrambling is performed by serially XORing the 8-bit (D0-D7) character with the 16-bit (D0-D15) output of the LFSR. An output of the LFSR, D15, is XORed with D0 of the data to be processed. The LFSR and data register are then serially advanced and the output processing is repeated for D1 through D7. The LFSR is advanced after the data is XORed.

The mechanism to notify the physical layer to disable scrambling is implementation specific and beyond the scope of this specification.

The data scrambling rules are as follows:

  • The LFSR implements the polynomial: G(X)=X16+X5+X4+X3+1
  • The LFSR value shall be advanced eight serial shifts for each Symbol except for SKP.
  • All 8b/10b D-codes, except those within the Training Sequence Ordered Sets shall be scrambled.
  • K codes shall not be scrambled.
  • The initialized value of an LFSR seed (D0-D15) shall be FFFFh. After COM leaves the Transmitter LFSR, the LFSR on the transmit side shall be initialized. Every time COM enters the Receive LFSR, the LFSR on the receive side shall be initialized. This also applies to the BRST sequence during loopback mode.

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8b/10b Decode Errors

An 8b/10b Decode error shall occur when a received Symbol does not match any of the valid 8b/10b Symbols listed. Any received 8b/10b Symbol that does not match any of thevalid 8b/10b Symbols listed shall be forwarded to the link layer by substituting aK28.4 symbol. 8b/10b errors may not directly initiate Recovery.

Special Symbols for Framing and Link Management

The 8b/10b encoding scheme provides Special Symbols that are distinct from the Data Symbols used to represent characters. These Special Symbols are used for various Link Management mechanisms described later. The table below lists the Special Symbols used and provides a brief description for each. Special Symbols must follow the proper 8b/10b disparity rules. The compliance tests are defined in the USB SuperSpeed Compliance Methodology white paper.

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Link Initialization and Training

Here we will discuss the sequences that are used for configuration and initialization. The sequences are used by the Initialization State Machine for the following functions:

  • Configuring and initializing the link
  • Bit-lock and symbol lock
  • Rx equalization training
  • Lane polarity inversion

Training sequences are composed of Ordered Sets used for initializing bit alignment, Symbol alignment and optimizing the equalization. Training sequence Ordered Sets are never scrambled but are always 8b/10b encoded.

Bit lock refers to the ability of the Clock/Data Recovery (CDR) circuit to extract the phase and frequency information from the incoming data stream. Bit lock is accomplished by sending a sufficiently long sequence of bits (D10.2 symbol containing alternating 0s and 1s) so the CDR roughly centers the clock within the bit.

Once the CDR is properly recovering data bits, the next step is to locate the start and end of a 10-bit symbol. For this purpose, the special K-Code called COMMA is selected from the 8b/10b codes. The bit pattern of the COMMA code is unique, so that it is never found in other data patterns, including any combination of a D-Code appended to any other D-Code or appended to any K-Code. This applies to any polarity of code. The only exception is for various bit patterns that include a bit error.

Training sequences (TS1 or TS2) are transmitted consecutively and can only be interrupted by SKP Ordered Sets occurring between Ordered Sets (between consecutive TS1 sets, consecutive TS2 sets, or when TS1 is followed by TS2).

Normative Training Sequence Rules

Training sequences are composed of Ordered Sets used for initializing bit alignment, symbol alignment, and receiver equalization.

The following rules apply to the training sequences:

  • Training sequence Ordered Sets shall be 8b/10b encoded.
  • Transmission of a TS1 or TS2 Ordered Set shall not be interrupted by SKP Ordered Sets. SKP Ordered Sets shall be inserted before, or after, completion of any TS1 or TS2 Ordered Set.
  • No SKP Ordered Sets are to be transmitted during the entire TSEQ time (65,536 ordered sets). This means that the PHY must manage elasticity buffer differently than during normal operation.

Training Control Bits

The training control bits are found in the Link Functionality symbol within the TS1 and TS2 ordered sets. Bit 0 and bit 2 of the link configuration field shall not be set to 1 simultaneously. If a receiver detects this condition in the received Link configuration field, then all of the training control bits shall be ignored.

Training Sequence Values

The TSEQ training sequence repeats 65,536 times to allow for testing many coefficient settings.

TSEQ Ordered Set

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TS1 Ordered Set

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TS2 Ordered Set

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Link Configuration Field

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Lane Polarity Inversion

During the TSEQ training sequence, the Receiver must use the D10.2 Symbol within the TSEQ Ordered Set to determine lane polarity inversion (Rxp and Rxn are swapped). If polarity inversion has occurred, the D10.2 symbols within the TSEQ ordered set will be received as D21.5 instead of D10.2 and the receiver must invert the polarity of the received bits. This must be done before the TSEQ symbols 1-15 are used since these symbols are not all symmetric under inversion in the 8b/10b domain. If the receiver does not use the TSEQ training sequence, then the polarity inversion may be checked against the D10.2 symbol in the TS1 ordered set.

Elasticity Buffer and SKP Ordered Set

The SuperSpeed architecture supports a separate reference clock source on each side of the SuperSpeed link. The accuracy of each reference clock is required to be within +-300 ppm. This gives a maximum frequency difference between the two devices of the link of +- 600 ppm. In addition, SSC creates a frequency delta that has a maximum difference of 5000 ppm. The total magnitude of the frequency delta can range from -5300 to 300 ppm. This frequency delta is managed by an elasticity buffer that consumes or inserts SKP ordered sets.

SKP Ordered Sets shall be used to compensate for frequency differences between the two ends of the link. The transmitter sends SKP ordered sets at an average of every 354 symbols. However, SKP ordered sets shall not be inserted within any packet. The transmitter is allowed to buffer the SKP ordered sets up to a maximum of four SKP ordered sets. The receiver must implement an elasticity buffer capable of buffering (or starving) eight symbols of data.

SKP Rules (Host/Device/Hub):

  • The SKP Ordered Set shall consist of a SKP K-Symbol followed by a SKP K-Symbol. A SKP Ordered Set represents two Symbols that can be used for clock compensation.
  • A device must keep a running count of the number of transmitted symbols since the last SKP Ordered set. The value of this count will be referred to as Y. The value of Y is reset whenever the transmitter enters Polling Active.
  • Unless otherwise specified, a transmitter shall insert the integer result of Y/354 calculation Ordered sets immediately after each transmitted TS1, TS2 Ordered Set, LMP, TP Data Packet Payload, or Logical idle. During training only, a transmitter is allowed the option of waiting to insert 2 SKP ordered sets when the integer result of Y/354 reaches 2. A transmitter shall not transmit SKP Ordered Sets at any other time.

Note: The non-integer remainder of the Y/354 SKP calculation shall not be discarded and shall be used in the calculation to schedule the next SKP Ordered Set.

  • SKP Commands do not count as interruptions when monitoring for Ordered Sets (i.e., consecutive TS1, TS2 Ordered Sets in Polling and Recovery).

Compliance Pattern

Entry to the Polling Compliance substate initiates the transmission of the pseudo-random data pattern generated by the scrambled D10.0 compliance sequence. SKPs are not sent during the compliance pattern. The compliance pattern shall be transmitted continuously or until a ping LFPS (refer to Section 6.9) is detected at the receiver. Upon detection of a ping LFPS, the compliance pattern shall advance to the next compliance pattern. Upon detection of a reset, LFPS the compliance pattern shall be terminated.

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Clock and Jitter

Informative Jitter Budgeting

The jitter for USB 3.0 is budgeted among the components that comprise the end to end connections: the transmitter, channel (including packaging, connectors, and cables), and the receiver. The jitter budget is derived at the silicon pads. The Dj distribution is the dual Dirac method.

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Normative Clock Recovery Function

The Tx Phase jitter measurement is performed using a standard clock recovery, shown in Figure 6-8. For information on the golden PLL measurement refer to the latest version of INCITS TR-35-2004, INCITS Technical Report for Information Technology – Fibre Channel – Methodologies for Jitter and Signal Quality Specification (FC-MJSQ).

The clock recovery function is given by Equations 1-3. A schematic of the general clock recovery function is shown in below. As shown, the clock recovery circuit has a low pass response. After the recovered clock is compared (subtracted) to the data, the overall clock recovery becomes a high pass function.

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The equations for these functions are:

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Where ωn is the natural frequency and ξ is the damping factor. The relationship to the 3 dB frequency is:

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As shown, the corner frequency 3ω dB =2π 10 and ζ = 0.707. This transfer function has a maximum peaking of 2 dB.

Normative Spread Spectrum Clocking (SSC)

All ports are required to have Spread Spectrum Clocking (SSC) modulation. Providing the same SSC clock to two different components is allowed but not required, the SSC can be generated asynchronously. The SSC profile is not specified and is vendor specific. The SSC modulation may not violate the phase slew rate.

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Normative Slew Rate Limit

The CDR is a slew rate limited phase tracking device. The combination of SSC and all other jitter sources within the bandwidth of the CDR must not exceed the maximum allowed slew rate. This measurement is performed by filtering the phase jitter with the CDR transfer function and taking the first difference of the phase jitter to obtain the filtered period jitter. The peak of the period jitter must not exceed TCDR_SLEW_MAX. Additional details on the slew rate measurement are available in USB 3.0 Jitter Budgeting.

Signaling

Eye Diagrams

The eye diagrams are a graphical representation of the voltage and time limits of the signal. This eye mask applies to jitter after the application of the appropriate jitter transfer function and reference receiver equalization. In all cases, the eye is to be measured for 106 consecutive UI. The budget for the link is derived assuming a total 10-12 bit error rate and is extrapolated to a measurement of 106 UI assuming the random jitter is Gaussian.

Below we see the eye mask used for all eye diagram measurements. The time is measured from the crossing points of Txp/Txn. The time is called the eye width, and the voltage is the eye height. The eye height is to be measured at the maximum opening (at the center of the eye width ± 0.05 UI).

The eye diagrams are to be centered using the jitter transfer function (JTF). The recovered clock is obtained from the data and processed by the JTF. The center of the recovered clock is used to position the center of the data in the eye diagram. The eye diagrams are to be measured into 50-Ω single-ended loads.

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Voltage Level Definitions

The differential voltage, VDIFF, is the voltage on Txp (Rxp at the receiver) with respect to Txn (Rxn at the receiver). VDIFF is the same voltage as the swing on the single signal of one conductor. The differential voltage is

(4) VDIFF = Txp – Txn

The total differential voltage swing is the peak to peak differential voltage, VDIFF-PP. This is twice the differential voltage. The peak to peak differential voltage is

(5) VDIFF-PP=2 * VDIFF

The Common Mode Voltage (VCM) is the average voltage present on the same differential pair with respect to ground. This is measured, with respect to ground, as

(6) VCM = (Txp + Txn) / 2

DC is defined as all frequency components below FDC = 30 kHz. AC is defined as all frequency components at or above FDC = 30 kHz. These definitions pertain to all voltage and current specifications.

In this waveform, the peak-to-peak differential voltage, VDIFF-PP is 800 mV. The differential voltage, VDIFF, is 400 mVPP. Note that while the center crossing point for both Txp and Txn is shown at 300 mV, the corresponding crossover point for the differential voltage is at 0.0 V. The center crossing point at 300 mV is also the common mode voltage, VCM. Note these waveforms include de-emphasis. The actual amount of de-emphasis can vary depending on the transmitter setting according to the allowed ranges below.

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Tx and Rx Input Parasitics

Tx and Rx input parasitics are specified by the lumped circuit shown below.

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In this circuit, the input buffer is simplified to a termination resistance in parallel with a parasitic capacitor. This simplified circuit is the load impedance.

Transmitter Specifications

Transmitter Electrical Parameters

Peak (p) and peak-peak (p-p) are defined below.

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The values are informative and not normative. They are included in this document to provide some guidance beyond the normative requirements for transmitter design and development. A transmitter can be fully compliant with the normative requirements of the specification and not meet all the values in this table (many of which are immeasurable in a finished product). Similarly, a transmitter that meets all the values in this table is not guaranteed to be in full compliance with the normative part of this specification.

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Low Power Transmitter

In addition to the full swing transmitter specification, an optional low power swing transmitter is also specified for SuperSpeed applications. A low power swing transmitter is typically used in systems that are sensitive to power and noise interference, and have a relative short channel. The requirement as to whether a transmitter needs to support full swing, low power swing, or both swings, is dependent on its usage model. All SuperSpeed transmitters must support full swing, while support for low power swing is optional. The method by which the output swing is selected is not defined in the specification, and is implementation specific. While two different transmitters are specified, only a single receiver specification is defined. This implies that receiver margins must be met if a low power transmitter is used.

Transmitter Eye

The eye mask is measured using the compliance data patterns (CP0 for DJ and CP1 for RJ). Eye height is measured for 106 consecutive UI. Jitter is extrapolated from 106 UI to 10-12 BER.

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The compliance testing setup is shown below. All measurements are made at the test point (TP1), and the Tx specifications are applied after processing the measured data with the compliance reference equalizer transfer function described in the next section.

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Tx Compliance Reference Receiver Equalize Function

The normative transmitter eye is captured at the end of the reference channel. At this point the eye may be closed. To open the eye so it can be measured a reference Rx equalizer, is applied to the signal. Details of the reference equalizer are contained below.

Informative Transmitter De-emphasis

The channel budgets and eye diagrams were derived using a VTX-DE-RATIO of transmit de-emphasis for both the Host and the Device reference channels. An example differential peak-to-peak de-emphasis waveform is shown below.

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Entry into Electrical Idle, U1

Electrical Idle is a steady state condition where the Transmitter Txp and Txn voltages are held constant at the same value and the Receiver Termination is within the range specified by ZRX-DC. Electrical Idle is used in the power saving state of U1.

The low impedance common mode and differential Receiver terminations values must be met in Electrical Idle. The Transmitter can be in either a low or high impedance mode during Electrical Idle.

Receiver Specifications

Receiver Equalization Training

The receiver equalization training sequence can be used to train the receiver equalizer. The TSEQ training sequence is designed to provide a spectrally rich data pattern that is useful for training typical receiver equalization architectures. In addition, a high edge density pattern is interleaved with the data to help the CDR maintain bit lock. The TSEQ training sequence repeats 65536 times to allow for testing many coefficient settings. No SKPs are inserted during the TSEQ training sequence. The frequency spectrum of the TSEQ sequence is shown in Figure 6-16.

Receiver equalization training is implementation specific.

Informative Receiver CTLE Function

USB 3.0 allows the use of receiver equalization to meet system timing and voltage margins. For long cables and channels the eye at the Rx is closed, and there is no meaningful eye without first applying an equalization function. The Rx equalizer may be required to adapt to different channel losses using the Rx EQ training period. The exact Rx equalizer and training method is implementation specific.

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Receiver Electrical Parameters

Normative specifications are to be measured at the connector. Peak (p) and peak- peak (p-p) are defined.

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The values are informative and not normative. They are included in this document to provide some guidance beyond the normative requirements for receiver design and development. A receiver can be fully compliant with the normative requirements of the specification and not meet all the values in this table (many of which are not measurable in a finished product). Similarly, a receiver that meets all the values in this table is not guaranteed to be in full compliance with the normative part of this specification.

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Receiver Loopback

The entry and exit process for receiver loopback.

Receiver loopback must be retimed. Direct connection from the Rx amplifier to the transmitter is not allowed for loopback mode. The receiver must continue to process SKPs as appropriate. SKP symbols must be consumed or inserted as required for proper clock tolerance compensation. Over runs or under runs of the clock tolerance buffers will reset the buffers to the neutral position.

During loopback the receiver must process the Bit Error Rate Test (BERT) commands. Loopback must occur in the 10-bit domain. No error correction is allowed. All symbols must be transmitted as received with the exception of SKP and BERT commands.

Loopback BERT

During loopback the receiver processes the BERT ordered sets BRST, BDAT, and BERC. BRST and BDAT are looped back as received. BERC ordered sets are not looped back but are replaced with BCNT ordered sets. Any time a BRST is received, the error count register EC is set to 0 and the scrambling LFSR is set to 0FFFFh. Any number of consecutive BRST ordered sets may be received.

BRST followed by BDAT starts the bit error rate test. The BDAT sequence is the output of the scrambler and is equivalent to the logical idle sequence. It consists of scrambled 0. The first 16 characters of the sequence are reprinted here:

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The receiver must compare the received data to the BDAT sequence. Errors increment the error count register (EC) by 1. EC may not roll over but must be held at FFh. The LFSR is advanced once for every character except SKPs. The LFSR rolls over after 216-1 symbols. SKPs must be inserted or deleted as necessary for clock tolerance compensation.

The BERC command does not increment the error count register. The LFSR is advanced. The BERC ordered set is replaced by the BCNT ordered set. The BCNT ordered set includes the nonscrambled 8b/10b encoded error count (EC) register based on the running disparity. Following the return of the BCNT ordered set, the loopback slave shall continue to repeat symbols as received.

BERC may be sent multiple times. The EC register is not cleared by BERC ordered sets.

BRST

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BDAT

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BERC

— IMAGE 39 —

BCNT

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Normative Receiver Tolerance Compliance Test

The receiver tolerance test is tested in the compliance reference channel. A pattern generator will send a compliance test pattern with added jitter through the compliance reference channels to the receiver. The receiver will loop back the data and any difference in the pattern sent from the pattern generator and returned will be an error. When running the compliance tests, the receiver should be put into loopback mode.

Additional details on the receiver compliance test are contained in the reference document, USB SuperSpeed Compliance Methodology.

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— IMAGE 42 —

The jitter components used to test the receiver shall meet the requirements below.

— IMAGE 43 —

Low Frequency Periodic Signaling (LFPS)

Low frequency periodic signaling (LFPS) is used for side band communication between the two ports across a link that is in a low power link state. It is also used when a link is under training, or when a downstream port issues Warm Reset to reset the link.

LFPS Signal Definition

Table 6-20 defines the LFPS electrical specification at the transmitter. tPeriod is the period of an LFPS cycle. An LFPS burst is the transmission of continuous LFPS signal over a period of time defined by tBurst. An LFPS sequence is defined by the transmission of a single LFPS burst of duration tBurst over a period of time defined by tRepeat. The link is in electrical idle between the two contiguous LFPS bursts.

An LFPS message is encoded based on the variation of tBurst. tRepeat is defined as a time interval when the next LFPS message is transmitted. The LFPS messages include Polling.LFPS and Ping.LFPS, as defined in Table 6-21. There are also LFPS signaling defined for U1/U2 and Loopback exit, U3 wakeup, and Warm Reset.

The detailed use of LFPS signaling is specified in the following sections and Chapter 7.

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— IMAGE 45 —

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Example LFPS Handshake for U1/U2 Exit, Loopback Exit, and U3 Wakeup

The LFPS signal used for U1/U2 exit, Loopback exit, and U3 wakeup is defined the same as continuous LFPS signals with the exception of timeout values. The handshake process for U1/U2 exit and U3 wakeup is shown below. The timing requirements are different for U1 exit, U2 exit, Loopback exit, and U3 wakeup.

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Note: the timing diagram is for illustration of the LFPS handshake process only.

The handshake process is as follows:

  • Link partner 1 initiates exit by transmitting LFPS at time t10. LFPS transmission shall continue until the handshake is declared either successful or failed.
  • Link partner 2 detects valid LFPS on its receiver and responds by transmitting LFPS at time t11. LFPS transmission shall continue until the handshake is declared either successful or failed.
  • A successful handshake is declared for link partner 1 if the following conditions are met within “tNoLFPSResponseTimeout” after t10:
  1. Valid LFPS is received from link partner 2.
  2. For U1 exit, U2 exit, U3 Wakeup and not Loopback exit, link partner 1 is ready to transmit the training sequences and the maximum time gap after an LFPS transmitter stops transmission and before a SuperSpeed transmitter starts transmission is 20 ns.

Note: There is no Near End Cross Talk (NEXT) specification for SuperSpeed transmitters and receivers. Therefore, when a port enters Recovery and starts transmitting TS1 Ordered Sets and its link partner is in electrical idle after successful LFPS handshake, a port may potentially train its receiver using its own TS1 Ordered Sets due to NEXT. The intention of adding the second exit condition is to prevent a port from electrical idle before transitioning to Recovery.

A successful handshake is declared for link partner 2 if the following conditions are met within tNoLFPSResponseTimeout after t11:

  1. Link partner 2 has transmitted the minimum LFPS defined as (t13 – t11).
  2. For U1 exit, U2 exit, U3 Wakeup, and not Loopback exit, link partner 2 is ready to transmit the training sequences and the maximum time gap after an LFPS transmitter stops transmission and before a SuperSpeed transmitter starts transmission is 20 ns.
  • A U1 exit, U2 exit, Loopback exit, and U3 wakeup handshake failure shall be declared if the conditions for a successful handshake are not met.
  • Link partner 1 shall declare a failed handshake if its successful handshake conditions were not met.
  • Link partner 2 shall declare a failed handshake if its successful handshake conditions were not met.

Note: Except for Ping.LFPS, when an upstream port in Ux or Loopback.Active receives an LFPS signal, it shall proceed with U1/U2 exit, or U3 wakeup, or Loopback exit handshake even if the LFPS is later determined to be a Warm Reset. If the LFPS is a Warm Reset, an upstream port, if in Ux, will enter Recovery and then times out to SS.Inactive, or if in Loopback Active, will enter Rx.Detect and then transitions to Polling.LFPS. When Warm Reset is detected, an upstream port will enter Rx.Detect

— IMAGE 48 —

Warm Reset

A Warm Reset is a reset generated only by a downstream port to an upstream port. A downstream port may issue a Warm Reset at any Link states except SS.Disabled. An upstream port is required to detect a Warm Reset at any link states except SS.Disabled.

A Warm Reset shares the same continuous LFPS signal as a low power Link state exit handshake signal. In order for an upstream port to be able to differentiate between the two signals, the tBurst of a Warm Reset is extended.

The Warm Reset assertion is asynchronous between a downstream port and an upstream port since it has to take a certain period of time for an upstream port to declare that a Warm Reset is detected.

However, the de-assertion of the Warm Reset between a downstream port and an upstream port must be made synchronous. Once a Warm Reset is issued by a downstream port, it will take at least tResetDelay for an upstream port to declare the detection of Warm Reset. Once a Warm Reset is detected, an upstream port must continue to assert the Warm Reset until it no longer receives any LFPS signals from a downstream port.

  • An upstream port shall declare the detection of Warm Reset within tResetDelay. The minimum tResetDelay shall be 18 ms; the maximum tResetDelay shall be 50 ms.

— IMAGE 49 —

Transmitter and Receiver DC Specifications

Informative ESD Protection

All signal and power pins must withstand 2000 V of ESD using the human body model and 500 V using the charged device model without damage (Class 2 per JEDEC JESE22-A114-A). This ESD protection mechanism also helps protect the powered down Receiver from potential common mode transients during certain possible reset or surprise insertion situations.

Informative Short Circuit Requirements

All Transmitters and Receivers must support surprise hot insertion/removal without damage to the component. The Transmitter and Receiver must be capable of withstanding sustained short circuit to ground of Txp (Rxp) and Txn (Rxn).

Normative High Impedance Reflections

During an asynchronous reset event, one device may be reset while the other device is transmitting. The device under reset is required to disconnect the receiver termination. During this time, the device under reset may be receiving active data. Since the data is not terminated, the differential voltage into the receiver will be doubled. For a short channel, the receiver may experience a total of 2* VDIFF.

The receiver must tolerate this doubling of the negative voltage that can occur if the Rx termination is disconnected. A part must tolerate a 20 ms event that doubles the voltage on the receiver input when the termination is disconnected 10,000 times over the life time of the part.

Receiver Detection

Rx Detect Overview

The Receiver Detection circuit is implemented as part of a Transmitter and must correctly detect whether a load impedance equivalent to a DC impedance RRX-DC (Table 6-13) is present. The Rx detection operates on the principle of the RC time constant of the circuit. This time constant changes based on the presence of the receiver termination. This is conceptually illustrated in Figure 6-23. In this figure, R_Detect is the implementation specific charging resistor. C_AC is the AC capacitor that is in the circuit only if R_Term is also present, otherwise, only C_Parasitic is present.

— IMAGE 50 —

The left side of the illustration shows the Receiver Detection circuit with no termination present. The right side of the figure is the same circuit with termination.

Detect voltage transition must be common mode. Detect voltage transition must conform to VTX_RCV_DETECT as described in Table 6-10.

The receiver detect sequence must be in the positive common mode direction only. Negative receiver detection is not allowed.

Rx Detect Sequence

The recommended behavior of the Receiver Detection sequence is:

  1. A Transmitter must start at a stable voltage prior to the detect common mode shift.
  2. A Transmitter changes the common mode voltage on Txp and Txn consistent with detection of Receiver high impedance which is bounded by parameter ZRX -HIGH-IMP-DC-POS listed in Table 6-13.
  3. A Receiver is detected based on the rate that the lines change to the new voltage.
  • The Receiver is not present if the voltage at the Transmitter charges at a rate dictated only by the Transmitter impedance and the capacitance of the interconnect and series capacitor.
  • The Receiver is present if the voltage at the Transmitter charges at a rate dictated by the Transmitter impedance, the series capacitor, the interconnect capacitance, and the Receiver termination.

Any time Electrical Idle is exited the detect sequence does not have to execute or may be aborted. During the Device connect, the Device receiver has to guarantee it is always in high impedance state while its power plane is stabilizing. This is required to avoid the Host falsely detecting the Device and starting the training sequence before the Device is ready. Similarly a disabled port has to keep its receiver termination in high impedance which is bounded by parameters ZRX -HIGH-IMP DCPOS until directed by higher layer to exit from the Disabled state. In contrast, a port which is at U1/U2/U3 Electrical Idle must have its Receiver Termination turned on and meet the RRX-DC specification.

Upper Limit on Channel Capacitance

The interconnect total capacitance to ground seen by the Receiver Detection circuit must not exceed 3 nF to ground, including capacitance added by attached test instrumentation. This limit is needed to guarantee proper operation during Receiver detect. Note that this capacitance is separate and distinct from the AC coupling capacitance value.

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